AVR32AP datasheet(31/181 Pages) ATMEL

31 / 181 page

32001A–AVR32–06/06

AVR32

Generally, all exceptions, including breakpoint, have the failing instruction as restart address.

This allows a fixup exception routine to correct the error and restart the instruction. Interrupts

(INT0-3, NMI) have the address of the first non-completed instruction as restart address. When

an event is accepted, the A1 stage and all upstream stages are flushed.

Branch folding complicates exception handling. If a folded instruction fails the condition check in

the A1 stage, the address of the folded instruction should be used as restart address. This is

implemented by passing the address of the folded instruction in the PC pipeline register.

When folding branches, both the branch and the folded instruction can be contaminated. How do

we determine which of the two instructions caused the exception? The fetch stage is responsible

for not folding instructions if the branch instruction is contaminated. The branch instruction can

be contaminated only due to instruction-address related exceptions, as it must already have

been decoded and recognized in order to have been placed in the BTB. This contamination is

known already in IF. If folding has occurred, it is guaranteed that the contamination was not in

the branch instruction, and it must therefore be in the folded instruction. Therefore, the folded

instruction should be restarted.

3.10.1

Event priority

Several instructions may be in the pipeline at the same time, and several events may be issued

in each pipeline stage. This implies that several pending exceptions may be in the pipeline

simultaneously. Priorities must therefore be imposed, ensuring that the correct event is serviced

first. The priority scheme obeys the following rules:

If several instructions trigger events, the instruction furthest down the pipeline is ser-

viced first, even if upstream instructions have pending events of higher priority.

If this instruction has several pending events, the event with the highest priority is ser-

viced first. After this event has been serviced, all pending events are cleared and the

instruction is restarted.

3.10.2

Exceptions and interrupt requests

When an event other than scall or debug request is received by the core, the following actions

are performed atomically:

The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM and

GM bits in the Status Register are used to mask different events. Not all events can be

masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit and Bus

Error) can not be masked. When an event is accepted, hardware automatically sets the

mask bits corresponding to all sources with equal or lower priority. This inhibits accep-

tance of other events of the same or lower priority, except for the critical events listed

above. Software may choose to clear some or all of these bits after saving the neces-

sary state if other priority schemes are desired. It is the event source’s responsability to

ensure that their events are left pending until accepted by the CPU.

When a request is accepted, the Status Register and Program Counter of the current

context is stored in the Return Status Register and Return Address Register corre-

sponding to the new context. Saving the Status Register ensures that the core is

returned to the previous execution mode when the current event handling is completed.

When exceptions occur, both the EM and GM bits are set, and the application may

manually enable nested exceptions if desired by clearing the appropriate bit. Each

exception handler has a dedicated handler address, and this address uniquely identi-

fies the exception source.

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