AVR32AP datasheet(27/181 Pages) ATMEL

27 / 181 page

32001A–AVR32–06/06

AVR32

Figure 3-4.

Forwarding destinations

3.9

Hazards not handled by the hardware

All hazards occurring between normal arithmetical, logical, load-store and change-of-flow

instructions are handled automatically by hardware. There are, however, a few instruction

sequences which must be sequenced by the user. These sequences are described in this chap-

ter. The programmer can assume that any instruction sequence other than the sequences

explicitly mentioned in this chapter will work without any special consideration.

3.9.1

Accessing system registers with mtsr and mfsr

The mtsr instruction writes the contents of a register into a system register. The system registers

control the behaviour of the CPU. The programmer must make sure that any mtsr instruction has

committed and has altered the state of the system in the desired way before issuing any new

instructions that depend on this new state. This can be done by inserting nop instructions, or

other instructions that do not depend on the new state generated by the mtsr instruction.

Table 2-2, “System Registers implemented in AVR32 AP,” on page 10 details the timing for

writes into the different system registers. The system registers are written as the mtsr instruction

leaves the pipeline stage described in the table. The system registers are read as the mfsr

instruction leaves the pipeline stage described in the table. As soon as a system register is read

by mfsr, it can be forwarded as any regular register file register.

Some of the system registers are located inside modules on the TCB bus. These are written

when the mtsr instruction leaves the D pipeline stage. Instructions depending on a mtsr to these

system registers being committed must therefore wait in the IS stage until the effects of the mtsr

is guaranteed to be visible to the instruction. The following code demonstrates a write to the

ASID field of TLBEHI, followed by a rete to an address which requires the new ASID to be visi-

ble. A nop is inserted to guarantee that the mtsr leaves the D stage at the same time as rete

leaves the A1 stage. In the following cycle, the icache will start fetching at the specified address

Integer unit

Load-store unit

Prefetch unit

Reg

File

Issue

Pointer

To cache

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