VT6306 datasheet(33/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-27-

Link Control Registers

Memory Offset DC – Fairness Control............................ RO

31-8 Reserved

........................................ always reads 0

7-0

Requests Per Fairness Interval

............... default = 0

The number of request packets allowed to be

transmitted per fairness interval

Memory Offset E0 (Set), E4 (Clear) – Link Control ..... RW

This register contains the control flags that enable and

configure the link core protocol portions of the chip.

contains controls for the receiver and cycle timer.

31-22 Reserved

........................................ always reads 0

Cycle Master

............................... default = undefined

Received cycle start packets will be accepted

to maintain synchronization with the node that

is sending them.

If the PHY has sent notification that it is root,

a cycle start packet will be generated every

time the cycle timer rolls over, based on the

setting of the “Cycle Source” bit.

This bit is cleared automatically if the “Cycle Too

Long” interrupt event occurs and cannot be set until

the “Cycle Too Long” interrupt event bit is cleared.

Cycle Timer Enable

.................... default = undefined

Cycle timer offset will not count

Cycle Timer offset will count cycles of the

24.576 MHz clock and roll over at the

appropriate time based on the settings of the

above bits

19-11 Reserved

........................................ always reads 0

Receive PHY Packet

................................. default = 0

All PHY packets received outside of the self-

ID phase are ignored

The receiver will accept incoming PHY

packets into the AR request context if the AR

request context is enabled. This bit does not

control receipt of self-ID packets.

Receive Self-ID

......................................... default = 0

All self-ID packets are ignored

The

receiver

will

incoming

self-

identification packets. Before setting this bit,

software must ensure that the self-ID buffer

pointer register contains a valid address.

8-0

Reserved

........................................ always reads 0

Memory Offset E8 – Node ID .......................................... RW

This register contains the CSR address for the node on which

this chip resides. The 16-bit combination of the Bus Number

and Node Number fields is referred to as the “Node ID”. The

Node Number field is updated when register 0 is sent from the

PHY. This can happen either because software requested a

read from the PHY through the PHY Control register or

because the PHY is sending the register (most likely due to a

bus reset).

ID Valid

No valid node number (cleared by bus reset)

Valid node number received from PHY

Root

This bit is set to 0 or 1 during bus reset

Attached PHY is not root .............................def

Attached PHY is root

29-28 Reserved

........................................always reads 0

Cable Power Status

PHY reports cable power status is not OK...def

PHY reports cable power status is OK.

26-16 Reserved

........................................always reads 0

15-6 Bus Number

................................... default = all ones

Used to identify the specific 1394 bus to which this

node belongs when multiple 1394-compatible buses

are connected via a bridge (set to 3FFh by bus reset)

5-0

Node Number

............................................default = 0

The physical node number established by the PHY

during self-identification and automatically set to the

value received from the PHY after the self-

identification phase. If the PHY sets this field to 63

(all ones), all link-level transmits are disabled.

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