 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADC3910CSSS bảng dữ liệu(PDF) 13 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC3910CSSS bảng dữ liệu(HTML) 13 Page - Texas Instruments |
|
|
13 / 131 page  5.10 Timing Requirements (continued) Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT INTERFACE TIMING - SERIAL CMOS tPD Propagation delay: sampling clock falling edge to output data delay Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge TS/4 + 3ns ns Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge TS/4 + 3ns tCD DCLK rising edge to output data delay 4 Lane serial CMOS Fout = 10 MSPS -7.25 -6.25 -5.25 ns Fout = 20 MSPS -4.125 -3.125 -2.125 Fout = 30 MSPS -3.08 -2.08 -1.08 DCLK rising edge to output data delay 2 Lane serial CMOS Fout = 5 MSPS -7.25 -6.25 -5.25 Fout = 10 MSPS -4.125 -3.125 -2.125 Fout = 15 MSPS -3.08 -2.08 -1.08 tDV Data valid, 4 Lane serial CMOS Fout = 10 MSPS -7.25 -6.25 -5.25 ns Fout = 20 MSPS -4.125 -3.125 -2.125 Fout = 30 MSPS -3.08 -2.08 -1.08 Data valid, 2 Lane serial CMOS Fout = 5 MSPS -7.25 -6.25 -5.25 Fout = 10 MSPS -4.125 -3.125 -2.125 Fout = 15 MSPS -3.08 -2.08 -1.08 SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input fCLK,SCLK Serial clock frequency 20 MHz tS,SEN SEN falling edge to SCLK rising edge 10 ns tH,SEN SCLK rising edge to SEN rising edge 10 tS,SDIO SDIO setup time from rising edge of SCLK 17 tH,SDIO SDIO hold time from rising edge of SCLK 9 SERIAL PROGRAMMING INTERFACE (SDIO) - Output tOZD Delay from falling edge of 8th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14 tOD Delay from falling edge of 8th SCLK cycle during read operation to SDIO valid 3.9 10.8 www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADC3910D125 |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
