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ADC3910CSSS bảng dữ liệu(PDF) 36 Page - Texas Instruments

tên linh kiện ADC3910CSSS
Giải thích chi tiết về linh kiện  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
PDF  131 Pages
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Trang chủ  http://www.ti.com
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ADC3910CSSS bảng dữ liệu(HTML) 36 Page - Texas Instruments

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6.3.6 Digital Features
6.3.6.1 Digital Down Converter
The ADC3910Dx and ADC3910Sx has an optional dual on-chip digital down converters (DDC) that can be
enabled via SPI register (0x0D4). It supports real decimation by 2, 4, 8, and 16. Real decimation operation is
illustrated with an example in Figure 6-9. The output data rate is decimated - a decimation of 8 would result in an
output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.
FS/2
FS/4
FS/8
FS/16
FS/32
Decima on by 2
Decima on by 4
Decima on by 8
Decima on by
16
Input Signal
Figure 6-9. Real decimation illustration, default
6.3.6.1.1 Digital Down Converter Data Select
Each digital comparator has the capability of selecting either channel with or without decimation data via SPI
write (0x200, 0x203).
ADC A
ADC B
N
N
Digital Downconverter
Figure 6-10. Digital down converter data multiplexer
6.3.6.1.2 Decimation Filter
The ADC3910Dx and ADC3910Sx has a stopband rejection of at least 70 dB, and a pass-band bandwidth of
approximately 80%. Table 6-2 gives an overview of the pass-band bandwidth of the different decimation settings
with respect to ADC sampling rate FS.
ADC3910D125
SBASAD1 – DECEMBER 2023
www.ti.com
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Product Folder Links: ADC3910D125



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