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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADC3910CSSS bảng dữ liệu(PDF) 57 Page - Texas Instruments |
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ADC3910CSSS bảng dữ liệu(HTML) 57 Page - Texas Instruments |
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57 / 131 page  Table 6-16. CLK_CFG_2 Register Field Descriptions Bit Field Type Reset Description 5:4 DCLKZ_RISE_DLY R/W 0h Adjust the delay on the rising edge of DCLKZ where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1) 3 RESERVED R 0h 2:1 DCLKZ_FALL_DLY R/W 0h Adjust the delay on the falling edge of DCLKZ where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1) 0 RESERVED R 0h 6.6.1.11 PDN_CFG Register (Address = 8Ch) [Reset = 00h] Return to the Summary Table. Table 6-17. PDN_CFG Register Field Descriptions Bit Field Type Reset Description 7 CHA_PDN R/W 0h Powers down ADC channel A. Reduces current by 12 mA. 0b = ADC channel A enabled 1b = ADC channel A powered down 6 CHB_PDN R/W 0h Powers down ADC channel B. Reduces current by 12 mA. 0b = ADC channel B enabled 1b = ADC channel B powered down 5 MASK_REF R/W 0h Fast power down mask control for reference amplifier. 0b = Reference amplifier powered down when fast power down is exercised. 1b = Reference amplifier NOT powered down when fast power down is exercised. 4 MASK_VCM R/W 0h Fast power down mask control for VCM buffer. 0b = VCM buffer powered down when fast power down is exercised. 1b = Reference amplifier NOT powered down when fast power down is exercised. 3 MASK_DLL R/W 0h Fast power down mask control for CLK DLL and DCLK DLL. 0b = DLLs powered down when fast power down is exercised. 1b = DLLs NOT powered down when fast power down is exercised. 2 SDR_CHB_SEL R/W 0h Selects the channel data to be sent out in SDR interface mode. Enable SDR with Channel B output when asserted. 0b = Channel A data 1b = Channel B data 1:0 RESERVED R 0h 6.6.1.12 DEV_CFG_3 Register (Address = 8Dh) [Reset = 00h] Return to the Summary Table. Table 6-18. DEV_CFG_3 Register Field Descriptions Bit Field Type Reset Description 6 FORMAT R/W 0h Output Data Format when digital features are bypassed. 0b = Two's Complement 1b = Offset binary 5:4 RESERVED R 0h www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: ADC3910D125 |
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