ADC3910CSSS datasheet(43/131 Pages) TI1

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6.3.6.2 Digital Comparator

The ADC3910Dx and ADC3910Sx has two internal digital comparators. The digital comparator controls the

output ALERT pin buffer. ALERT pin can be configured as open-drain or push-pull using the ALERT_OD (0x090)

CHA 10-bit data/DDC data

High threshold

- Hysteresis

Low threshold

+ Hysteresis

ALERT

CHB 10-bit data/DDC data

DWC0 DATA

SEL[2:0]

DWC0

CONFIG

SEL[0]

ALERT_FLAG

Event

Counter

EVENT_FLAG

Window Size [15:0]

ALERT_CFG

EVENT_CFG

Figure 6-24. Digital Comparator Block Diagram

6.3.6.2.1 Comparator Data Select

Each digital comparator has the capability of selecting either channel with or without decimation data via SPI

write (0x201, 0x203).

Comparator

ALERT

ADC A

ADC B

Channel

Correction

Channel

Correction

Figure 6-25. Comparator multiplexer

6.3.6.2.2 Comparator High and Low Threshold

The

digital

comparator

high-side

threshold,

low-side

threshold

and

hysteresis

(optional)

parameters are independently programmed for each digital comparator (COMP_THRESHOLD_HI_CHx,

COMP_THRESHOLD_LO_CHx, COMP_HYSTERESIS_CHx) via SPI write to registers 0x0C8-0x0D3.

6.3.6.2.3 Comparator Configuration Compare Mode

The digital comparator can be configured to either standard compare or slew compare via SPI write SLEW_CHx

(0x0D3).

Standard Compare level based:

• COMP_THRESHOLD_HI_CHx - COMP_HYSTERESIS_CHx

• COMP_THRESHOLD_LO_CHx + COMP_HYSTERESIS_CHx

Slew Compare to detect based on difference between subsequent samples:

• Current sample - Previous sample > COMP_THRESHOLD_HI_CHx

• Current sample - Previous sample < COMP_THRESHOLD_LO_CHx

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ADC3910D125

SBASAD1 – DECEMBER 2023

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