USB97C102 datasheet(66/80 Pages) SMSC

66 / 80 page

SMSC DS – USB97C102

Page 66

Rev. 03/23/2000

HubControl1

(0x7FA6- RESET=0x00)

HUB CONTROL REGISTER1

BIT

NAME

R/W

DESCRIPTION

HubBypass3

R/W

When this bit is set(1), Ports 1 and 3 are no longer connected to the hub.

Port 1 (which is connected to the rest of the 97C102) is connected to port

3. Port 3 becomes the upstream of Port 1. See figure on next page. See

Note1.

HubBypass2

R/W

When this bit is set(1), Ports 1 and 2 are no longer connected to the hub.

Port 1 (which is connected to the rest of the 97C102) is connected to port

2. Port 2 becomes the upstream of Port 1. See figure on next page. See

Note1.

ForceSE0

R/W

Force Single Ended zero (SE0). – This bit will force a SE0 condition on the

upstream port of Port 1 (as selected by the Host_EmuX bits). It is the

responsibility of the 8051 MCU to make sure the duty cycle of the SE0

assertion is within the USB specified range for the intended operation

(EOP = exactly 2 low speed periods; Disconnect > 2.5µs).

GangedPWR

R/W

Ganged Power Sense enable – When this bit is set (1), the Power Control

block of the HUB Compound device will internally OR the power OK sense

pins (nPWROK[5:2]) and Power Enable (nPWREN[5:2]) pins. This will

allow the system designer the ability to reduce implementation costs by

reducing the external current hardware. In this mode, since only one

Sense and Enable PIN is required, the unused input pins must be tied to

VDD (1) and the unused output pins may be left unconnected.

Note 1: When the SMSC USB97C102 is in “HubBypass” mode, all other ports, with the HubBypass bit cleared (0),

are still connected to the internal USB Hub. Please refer to FIGURE 8 – HUBBYPASS2 on page 67 for a diagram

showing “HubBypass” mode. It is recommended that only one “HubBypass” bit be set.

USB97C102 bảng dữ liệu(PDF) 66 Page - SMSC Corporation