USB97C102 datasheet(35/80 Pages) SMSC

35 / 80 page

SMSC DS – USB97C102

Page 35

Rev. 03/23/2000

Table 51 - Channel 3 Byte Count Register

CH3_CNT

(ISA 0x0007)

CHANNEL 3 BYTE COUNT

BIT

NAME

R/W

DESCRIPTION

[7:0]

CH3_CNTL

R/W

Lower 8 bits of Byte Count when Byte F/F = 0

[7:0]

CH3_CNTH

R/W

Upper 8 bits of Byte Count when Byte F/F = 1

Note:

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See Address Programming Table for 16 bit Address definitions.

Table 52 - Channel Status Register

CH_STAT

(ISA 0x0008)

CHANNEL STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

CH3RQ

Channel 3 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH2RQ

Channel 2 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH1RQ

Channel 1 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH0RQ

Channel 0 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH3TC

Channel 3 Terminal Count Reached

0 = No

1 = Yes

CH2TC

Channel 2 Terminal Count Reached

0 = No

1 = Yes

CH1TC

Channel 1 Terminal Count Reached

0 = No

1 = Yes

CH0TC

Channel 0 Terminal Count Reached

0 = No

1 = Yes

Note 1: These bits are also visible outside of I/O space in the BUS_STAT register.

Note 2: These bits are cleared when this register is read through the ISA I/O Window.

Table 53 - 8237 Command Register

CH_CMD

(ISA 0x0008)

COMMAND REGISTER

BIT

NAME

R/W

DESCRIPTION

DACK_SENS

DACK Sense

0 = Active High

1 = Active Low

DREQ_SENS

DREQ Sense (1 = Active Low, 0 = Active High)

WRITE_TIME

Write Timing Select

0 = Late Timing

1 = Extended

PRIORITY

Priority

0 = Fixed

1 = Rotating

COMP_TIME

Timing

0 = Normal

1 = Compressed

CTRL_EN

Controller Enable

0 = Enable

1 = Disable

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