USB97C102 datasheet(28/80 Pages) SMSC

28 / 80 page

SMSC DS – USB97C102

Page 28

Rev. 03/23/2000

Table 33 - Wakeup Mask 1 Register

WU_MSK_1 (Note 1)

(0x7F2B - RESET=0x07 )

WAKEUP MASK 1

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

USB_Reset

R/W

External wakeup event.

0 = Enabled

1 = Masked

Resume

R/W

External wakeup event.

0 = Enabled

1 = Masked

Suspend

R/W

Internal wakeup event.

0 = Enabled

1 = Masked

Suspend – If 3ms of IDLE state are detected by the hardware,

then this bit, when set (1) will cause an interrupt to the MCU

Note 1: Interrupt events enabled by these bits are routed to the PWR_MNG Bit 0 in the ISR_1 register.

Table 34 - Wakeup Source 2 Register

WU_SRC_2

(0x7F2C - RESET=0x00)

WAKEUP SOURCE 2

BIT

NAME

R/W

DESCRIPTION

[7:4]

'0'

R/W

Reserved

IRQ3

R/W

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ2

R/W

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ1

R/W

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

IRQ0

R/W

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

Note 1: Any transition from high to low, or low to high on the associated input sets these bits.

Note 2: The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Note 3: Since this register will report any status change, when devices are to be powered down while monitored, the

appropriate bits must be masked until the device is armed correctly.

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