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AMC131M02DFMR bảng dữ liệu(PDF) 49 Page - Texas Instruments

tên linh kiện AMC131M02DFMR
Giải thích chi tiết về linh kiện  AMC131M02 2-Channel, 64-kSPS, Simultaneous-Sampling, 24-Bit, Reinforced Isolated Delta-Sigma ADC With Integrated DC/DC Converter
PDF  89 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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AMC131M02DFMR bảng dữ liệu(HTML) 49 Page - Texas Instruments

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DRDY
CS
SCLK
DOUT
CRC
Data
Data
Hi-Z
Status
CRC
Data
Time where data is
not being read
SYNC Pulse
SYNC / RESET
Figure 8-29. Collecting Data After a Pause Using the SYNC/RESET Pin
Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by
reading two samples in quick succession. Figure 8-30 shows this method. This example shows that when the
DRDY_FMT bit in the MODE register is set to 0b, DRDY is a level output. There is a very narrow pulse on
DRDY immediately after the first set of data are shifted out of the device. This pulse can be too narrow for some
microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the second
data set after the first data set. The host operates synchronous to the device after the second word is read from
the device.
DRDY
CS
SCLK
DOUT
CRC
Data
Data
Hi-Z
Status
CRC
Data
Status
CRC
Data
Time where data is
not being read
Narrow DRDY Pulse
Data is read a
second time
Figure 8-30. Collecting Data After a Pause by Reading Data Twice
www.ti.com
AMC131M02
SBASA56 – SEPTEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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