AMC131M02DFMR datasheet(27/89 Pages) TI

27 / 89 page

The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register

corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit, two's-

complement value corresponding to the number of modulator clock cycles of phase offset compared to a

reference phase of zero degrees.

The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces

samples continuously at the modulator frequency, fMOD. These samples are filtered and decimated to the output

data rate by the digital filter. The ratio between fMOD and the data rate is the oversampling ratio (OSR). Each

conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the

different channels of the AMC131M02 have no programmed phase offset between them, the modulator clock

cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure

8-11 shows an example scenario where the voltage input to channel 1 has no phase offset from channel 0.

CH0 Input

Sample

Period

CH1 Input

Figure 8-11. Two Channel Outputs With Equal Phase Settings

However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels

are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same

time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-12

shows how the period corresponding to the samples are shifted between channels. Figure 8-13 illustrates how

the samples appear as having generated a phase shift when retrieved by the host.

CH0 Input

Sample

Period

CH1 Input

Sample Period

Offset

Figure 8-12. Channel 1 With a Positive Sample Phase Shift With Respect to Channel 0

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AMC131M02

SBASA56 – SEPTEMBER 2023

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AMC131M02DFMR bảng dữ liệu(PDF) 27 Page - Texas Instruments