AMC131M02DFMR datasheet(42/89 Pages) TI

42 / 89 page

8.5.2 ADC Conversion Data

The device provides conversion data for each channel at the data rate set by the OSR bits in the CLOCK

calibration setting and the DRDY_SEL[1:0] bits in the MODE register when in continuous-conversion mode.

All data are available immediately following DRDY assertion in global-chop mode. The conversion status of all

channels is available as the DRDY[1:0] bitsin the STATUS register. The STATUS register content is automatically

output as the response to the NULL command.

Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size.

The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the

setting of the WLENGTH[1:0] bits in the MODE register.

Data are given in binary two's-complement format. Use Equation 10 to calculate the size of one code (LSB).

1 LSB = (2.4 V / Gain) / 224 = +FSR / 223

(10)

A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 V / Gain – 1 LSB produces an output code of 7FFFFFh, and

a negative full-scale input (VIN ≤ –FSR = –1.2 V / Gain) produces an output code of 800000h. The output clips at

these codes for signals that exceed full-scale.

Table 8-10 summarizes the ideal output codes for different input signals.

Table 8-10. Ideal Output Code versus Input Signal

INPUT SIGNAL,

VIN = VAINP – VAINN

IDEAL OUTPUT CODE

≥ FSR (223 – 1) / 223

7FFFFFh

FSR / 223

000001h

000000h

–FSR / 223

FFFFFFh

≤ –FSR

800000h

Figure 8-23 shows the mapping of the analog input signal to the output codes.

7FFFFFh

Input Voltage V

7FFFFEh

000001h

000000h

800000h

FFFFFFh

800001h

Figure 8-23. Code Transition Diagram

AMC131M02

SBASA56 – SEPTEMBER 2023

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