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AT83SND2CMP3B bảng dữ liệu(PDF) 167 Page - ATMEL Corporation |
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AT83SND2CMP3B bảng dữ liệu(HTML) 167 Page - ATMEL Corporation |
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167 / 241 page ![]() 167 4341F–MP3–03/06 AT8xC51SND2C/MP3B Table 19-3. SPSTA Register SPSTA (S:C4h) – SPI Status Register Reset Value = 00000 0000b Table 19-4. SPDAT Register SPDAT (S:C5h) – Synchronous Serial Data Register Reset Value = XXXX XXXXb 76 543 210 SPIF WCOL - MODF - - - - Bit Number Bit Mnemonic Description 7 SPIF SPI Interrupt Flag Set by hardware when an 8-bit shift is completed. Cleared by hardware when reading or writing SPDAT after reading SPSTA. 6WCOL Write Collision Flag Set by hardware to indicate that a collision has been detected. Cleared by hardware to indicate that no collision has been detected. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4MODF Mode Fault Set by hardware to indicate that the SS pin is at an appropriate level. Cleared by hardware to indicate that the SS pin is at an inappropriate level. 3 - 0 - Reserved The value read from these bits is indeterminate. Do not set these bits. 76 543 210 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Bit Number Bit Mnemonic Description 7 - 0 SPD7:0 Synchronous Serial Data. |
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