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AT83SND2CMP3B bảng dữ liệu(PDF) 166 Page - ATMEL Corporation

tên linh kiện AT83SND2CMP3B
Giải thích chi tiết về linh kiện  Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
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AT83SND2CMP3B bảng dữ liệu(HTML) 166 Page - ATMEL Corporation

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4341F–MP3–03/06
AT8xC51SND2C/MP3B
19.4
Registers
Table 19-2.
SPCON Register
SPCON (S:C3h) –
SPI Control Register
Reset Value = 0001 0100b
Note:
1. When the SPI is disabled, SCK outputs high level.
76
543
210
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit
Mnemonic
Description
7SPR2
SPI Rate Bit 2
Refer to Table 19-1 for bit rate description.
6
SPEN
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
5
SSDIS
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no effect if
CPHA = 0.
Clear to enable SS in both master and slave modes.
4MSTR
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
3CPOL
SPI Clock Polarity Bit(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
2CPHA
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
1 - 0
SPR1:0
SPI Rate Bits 0 and 1
Refer to Table 19-1 for bit rate description.



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