IP101G-DS-R01 datasheet(38/65 Pages) ETC

38 / 65 page

IP101G

Data Sheet

38/65

January 14, 2014

IP101G-DS-R01

MII page17 register17

page

MII

ROM R/W

Description

Default

17[1]

RO/

WOL_PLUS_SLEEP

WOL+ sleep status.

This bit is a latched high signal that provide a previous status

for WOL+ sleep mode.

Master mode:

IP101G has entered WOL+ sleep mode.

Slave mode:

IP101G is ready for entering WOL+ sleep mode.

17[0]

RO/

WOL_PLUS_WAKE

WOL+ wake status.

This bit is a latched high signal that provide a previous status

for WOL+ wake up.

Master mode:

=IP101G has left WOL+ sleep mode.

Slave mode:

=IP101G is ready for wake up.

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

Example 1, Read page3 register16 (Read Data from page3 register16 of PHY address 0):

Write 0.20 = 0x0003 //page3

//Read Data from page3 register16

Write 0.20 = 0x0000 //restore to page0

Example 2, Write page3 register16 = 0x3400 (Write Data 0x3400 to page3 register16 of PHY address 0):

Write 0.20 = 0x0003 //page3

Write 0.16 = 0x3400 //Write Data 0x3400 to page3 register16

Write 0.20 = 0x0000 //restore to page0

4.8 UTP PHY Specific Control Register

MII page1 register22

page

MII

ROM R/W

Description

Default

Linear Regulator Output Control Register

22[15]

R/W LDO Output Disable

1: LDO Output Disable

0: LDO Output Enable

(e-fuse)

22[14:0]

R/W Reserved

0x2020

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

MII page1 register23

page

MII

ROM R/W

Description

Default

UTP PHY Specific Control Register

23[15:14]

R/W Reserved

2’b10

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