LAN9218 datasheet(31/130 Pages) SMSC

tên linh kiện	LAN9218

Giải thích chi tiết về linh kiện	High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX

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High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

SMSC LAN9218

Revision 1.5 (07-18-06)

DATASHEET

The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is

disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used

to monitor internal MII signals.

3.10.2.1

Supported EEPROM Operations

The EEPROM controller supports the following EEPROM operations under host control via the

E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A

description and functional timing diagram is provided below for each operation. Please refer to the

E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on

page 90 for E2P_CMD field settings for each command.

ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will

erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the

EEPROM does not respond within 30ms.

Figure 3.2 EEPROM Access Flow Diagram

Idle

Write Data

Write

Command

Read

Command

Busy Bit = 0

Idle

Write

Command

Read

Command

Read Data

Busy Bit = 0

EEPROM Write

EEPROM Read

LAN9218 bảng dữ liệu(PDF) 31 Page - SMSC Corporation