STE10A datasheet(51/82 Pages) STMICROELECTRONICS

51 / 82 page

STE10/100A

Registers and descriptors description

51/82

2JCLK

Jabber clock

0: cut off transmission after 2.6 ms (100Mbps) or

26 ms (10Mbps).

1: cut off transmission after 2560 byte-time.

1NJ

Non-Jabber

0: if jabber expires, re-enable transmit function

after 42 ms (100Mbps) or 420ms (10Mbps).

1: immediately re-enable the transmit function

after jabber expires.

0JBD

Jabber disable

1: disable transmit jabber function

CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2)

TEIS

Transmit early interrupt status

Transmit early interrupt status is set to 1 when

TEIE (bit 31 of CSR17 set) is enabled and the

transmitted packet is moved from descriptors to

the TX-FIFO buffer. This bit is cleared by writing

a 1.

0RO/LH*

REIS

Receive early interrupt status.

Receive early interrupt status is set to 1 when

REIE (CSR17 bit 30) is enabled and the

received packet has filled up its first receive

descriptor. This bit is cleared by writing a 1.

0RO/LH*

XIS

Transceiver (XCVR) interrupt status. Formed by

the logical OR of XR8 bits 6~0.

1RO/LH*

TDIS

Transmit deferred interrupt status.

RO/LH*

---

Reserved

PFR

PAUSE frame received interrupt status.

1: indicates receipt of a PAUSE frame while the

PAUSE function is enabled.

0RO/LH*

25~ 23

BET

Bus error type. This field is valid only when FBE

(CSR5 bit 13, fatal bus error) is set. There is no

interrupt generated by this field.

000: parity error, 001: master abort, 010:

target abort.

011, 1xx: reserved

000

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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