STE10A datasheet(70/82 Pages) STMICROELECTRONICS

tên linh kiện	STE10A

Giải thích chi tiết về linh kiện	PCI 10/100 Ethernet controller with integrated PHY (3.3V)

PDF	82 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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General EEPROM format description

STE10/100A

70/82

General EEPROM format description

Table 15.

Connection type definition

Offset

Length

Description

STE10/100A signature: 0x81, 0x09

Format major version: 0x02,

old ROM format version 0x01 is for STE10/100A-MAC only.

Format minor version: 0x00

Reserved

IEEE network address: ID1, ID2, ID3, ID4, ID5, ID6

IEEE ID checksum1:

Sm0=0, carry=0

SUM=Sm6 where Smi=(Smi-1<<1)+(carry from shift)+IDi

IEEE ID checksum2:

Reserved, should be zero.

PHY type, 0xFF: Internal PHY (STE10/100A only)

Reserved, should be zero

Default connection type, see Table 15

Reserved, should be zero

Flow control field,

00: Disable flow control function,

01: Enable flow control function.

PCI device ID

PCI vendor ID

PCI subsystem ID

PCI subsystem vendor ID

MIN_GNT value

MAX_LAT value

Cardbus CIS pointer

CSR18 (CR) bit 31-16 recall data

Reserved, should be zero

CheckSum, the least significant two bytes of FCS for data stored in offset

0..7D of EEPROM

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