STE10A datasheet(42/82 Pages) STMICROELECTRONICS

42 / 82 page

Registers and descriptors description

STE10/100A

42/82

CSR5 (offset = 28h), SR - Status register

31~ 26

----

Reserved

25~ 23

BET

Bus error type. This field is valid only when bit 13

of CSR5(fatal bus error) is set. There is no

interrupt generated by this field.

000: parity error, 001: master abort, 010:

target abort

011, 1xx: reserved

000

22~ 20

Transmit state. Reports the current transmission

state only, no interrupt will be generated.

000: stop

001: read descriptor

010: transmitting

011: FIFO fill, read the data from memory and

put into FIFO

100: reserved

101: reserved

110: suspended, unavailable transmit descriptor

or FIFO overflow

111: write descriptor

000

19~17

Receive state. Reports current receive state

only, no interrupt will be generated.

000: stop

001: read descriptor

010: check this packet and pre-fetch next

descriptor

011: wait for receiving data

100: suspended

101: write descriptor

110: flush the current FIFO

111: FIFO drain, move data from receiving FIFO

into memory

000

NISS

Normal interrupt status summary. Set if any of

the following bits of CSR5 are asserted:

–

TCI, transmit completed interrupt (bit

–

TDU, transmit descriptor unavailable

(bit 2)

–

RCI, receive completed interrupt (bit

0RO/LH*

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

STE10A bảng dữ liệu(PDF) 42 Page - STMicroelectronics

STE10A bảng dữ liệu(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

bảng dữ liệu tải về

Link URL