STE10A datasheet(34/82 Pages) STMICROELECTRONICS

34 / 82 page

Registers and descriptors description

STE10/100A

34/82

CR3 (offset = 0ch), LT - Latency timer

31~16

---

Reserved

15~ 8

Latency timer. This value specifies the latency timer

of the STE10/100A in units of PCI bus clock cycles.

Once the STE10/100A asserts FRAME#, the latency

timer starts to count. If the latency timer expires and

the STE10/100A is still asserting FRAME#, the

STE10/100A will terminate the data transaction as

soon as its GNT# is removed.

40h

R/W

7 ~ 0

CLS

Cache line size. This value specifies the system

cache line size in units of 32-bit double words (DW).

The STE10/100A supports cache line sizes of 8, 16,

or 32 DW. CLS is used by the STE10/100A driver to

program the cache alignment bits (bit 14 and 15 of

CSR0) which are used for cache oriented PCI

commands, for example, memory-read-line,

memory-read-multiple, and memory-write-and-

invalidate.

08h

R/W

CR4 (offset = 10h), IOBA - I/O base address

31~ 7

IOBA

I/O base address. This value indicate the base

address of PCI control and status register

(CSR0~28), and transceiver registers (XR0~10).

0R/W

6 ~ 1

---

Reserved

0IOSI

I/O space indicator.

1: means that the configuration registers map into

I/O space.

1RO

CR5 (offset = 14h), MBA - Memory base address

31~ 7

MBA

Memory base address. This value indicate the base

address of PCI control and status

registers(XR0~10).

0R/W

6 ~ 1

---

Reserved

0IOSI

Memory space indicator.

1: means that the configuration registers map into

I/O space.

0RO

CR11 (offset = 2ch), SID - Subsystem ID

31~16

SID

Subsystem ID. This value is loaded from EEPROM

as a result of power-on or hardware reset.

From

EEPROM

15~ 0

SVID

Subsystem vendor ID. This value is loaded from

EEPROM as a result power-on or hardware reset.

From

EEPROM

CR12 (offset = 30h), BRBA - Boot ROM base address. This register should be initialized before

accessing the boot ROM space.

Table 6.

Configuration registers description (continued)

Bit #

Name

Description

Default

RW type

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