M58BW16F datasheet(29/81 Pages) STMICROELECTRONICS

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M58BW16F, M58BW32F

Bus operations

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3.3.3

X-Latency Bits (M13-M11)

The X-Latency bits are used during Synchronous Bus Read operations to set the number of

clock cycles between the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 8: Burst

Configuration Register.

3.3.4

Y-Latency Bit (M9)

The Y-Latency bit is used during Synchronous Bus Read operations to set the number of

clock cycles between consecutive reads. The Y-Latency value depends on both the X-

Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each clock cycle.

3.3.5

Valid Data Ready Bit (M8)

The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When

the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the rising

clock edge when invalid data is output on the bus.

3.3.6

Wrap Burst Bit (M3)

Burst read can be confined inside the 4 double-word boundary (wrap) or overcome the

boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The

wrap mode is not available (M3 is always ‘1’).

3.3.7

Burst Length Bit (M2-M0)

The Burst Length bits set the maximum number of Double-Words that can be output during

a Synchronous Burst Read operation. Burst lengths of 4 or 8 are available.

Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits

that the memory accepts.

If a Burst Read operation (no wrap) has been initiated the device will output data

synchronously. Depending on the starting address, the device activates the Valid Data

Ready output to indicate that a delay is necessary before the data is output. If the starting

address is aligned to a 4 double word boundary, the 8-double-word burst mode will run

without activating the Valid Data Ready output. If the starting address is not aligned to a 4

Double Word boundary, Valid Data Ready is activated to indicate that the device needs an

internal delay to read the successive words in the array.

M10, M7 to M4 are reserved for future use.

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