M58BW16F datasheet(21/81 Pages) STMICROELECTRONICS

21 / 81 page

M58BW16F, M58BW32F

Signal descriptions

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2.5

Output Disable (GD)

The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at

VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the

outputs are high impedance independently of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as there is no internal pull-up resistor to drive

the pin.

2.6

Write Enable (W)

The Write Enable, W, input controls writing to the Command Interface, Input Address and

Data latches. Both addresses and data can be latched on the rising edge of Write Enable

(also see Latch Enable, L).

2.7

Reset/Power-Down (RP)

The Reset/Power-Down, RP, is used to apply a hardware reset to the memory. A hardware

reset is achieved by holding Reset/Power-Down Low, VIL, for at least tPLPH. Writing is

inhibited to protect data, the Command Interface and the Program/Erase Controller are

reset. The Status Register information is cleared and power consumption is reduced to the

standby level (IDD1). The device acts as deselected, that is the data outputs are high

impedance.

After Reset/Power-Down goes High, VIH, the memory will be ready for Bus Read operations

after a delay of tPHEL or Bus Write operations after tPHWL.

If Reset/Power-Down goes Low, VIL, during a Block Erase or a Program operation, the

operation is aborted, in a time of tPLRH maximum, and data is altered and may be corrupted.

During Power-up power should be applied simultaneously to VDD and VDDQ(IN) with RP held

at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E,

and Write Enable, W, should be held at VIH during power-up.

In an application, it is recommended to associate the Reset/Power-Down pin, RP, with the

reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory

is performing an erase or program operation, the memory may output the Status Register

information instead of being initialized to the default Asynchronous Random Read mode.

See Table 22 and Figure 21: Reset, Power-Down and Power-up AC waveform, for more

details.

2.8

Program/Erase Enable (PEN)

The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase

operations from modifying the data.

Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to

High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is

generated in the Status Register.

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