UPD6P9 datasheet(33/73 Pages) RENESAS

33 / 73 page

µPD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

6. RESET

A system reset is effected by the following causes:

• When the POC circuit has detected low power-supply voltage

• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed

• When the accumulator is 0H when the RLZ instruction is executed

• When stack pointer overflows or underflows

Table 6-1. Hardware Statuses After Reset

Hardware

• Reset by On-Chip POC Circuit During Operation

• Reset by the On-Chip POC Circuit During

• Reset by Other FactorsNote 1

Standby Mode

PC 11 bits:

µPD67, 67A, 000H

68, 68A

12 bits:

µPD69

SP (1 bit)

Data

R0 = DP

000H

memory

R1 to RF

Undefined

Accumulator (A)

Undefined

Status flag (F)

Carry flag (CY)

Timer (10 bits)

000H

Port register

FFH

×××× 11×1BNote 2

Control register P3

0000

×000BNote 3

26H

Notes 1. The following resets are available.

• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

• Reset when executing the RLZ instruction (when A = 0)

• Reset by stack pointer’s overflow or underflow

×: Refers to the value by the KI or S2 pin status.

In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when

POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor

connected).

×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID).

Remark VID: RAM retention detection voltage

UPD6P9 bảng dữ liệu(PDF) 33 Page - Renesas Technology Corp

UPD6P9 bảng dữ liệu(HTML) 33 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

bảng dữ liệu tải về

Link URL