S32K310 datasheet(89/136 Pages) NXP

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Table 44. LPSPI (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tHO

Data hold time

(outputs)

-18

—

Master_10Mbps, for

S32K3x8

tHO

Data hold time

(outputs) 4

-2

—

Master Loopback

tRI/FI

Rise/Fall time input

—

Slave

tFI/RI

Rise/Fall time input

—

Master

tFI/RI

Rise/Fall time input 4 —

—

Master Loopback

tFO/RO

Rise/Fall time output —

—

Slave

tFO/RO

Rise/Fall time output —

—

Master

tFO/RO

Rise/Fall time

output 4

—

Master Loopback

1. tperiph = 1/fperiph

2. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.

3. fperiph = LPSPI peripheral clock

4. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting

LPSPI_CFGR1[SAMPLE] bit as 1.

5. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated

in the table below. Unless otherwise noted, all other ‘master’ and ‘slave’ specifications are also applicable in the 10Mbps

configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.

6. LPSPI0 support up to 20MHz on fast pin.

7. Minimum configuration value for CR[PCSSCK] field is 3(0x00000011).

8. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).

9. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.

fperiph = LPSPI peripheral clock

MSB OUT2

LSB OUT

BIT 6 ... 1

MSB IN2

SS1

(OUTPUT)

SPSCK

(CPOL = 0)

(OUTPUT)

SPSCK

(CPOL = 1)

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

LSB IN

BIT 6 ... 1

Figure 40. LPSPI Master Mode Timing (CPHA=0)

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 8, 06/2023

Data Sheet: Technical Data

Preliminary Information for S32K3x8

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