S32K310 datasheet(83/136 Pages) NXP

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Table 41. PLL (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

JPLL_acc

PLL accumulated

jitter (pk-pk) 1,2,3

—

1680

FPLL_out = 240MHz,

Fractional Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1,2,3

—

295

FPLL_out = 160MHz,

Integer Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1,2,3

—

670

FPLL_out = 160MHz,

Fractional Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1,2,3

—

840

FPLL_out = 160MHz,

Integer Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1,2,3

—

1680

FPLL_out = 160MHz,

Fractional Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1,2,3

—

353

FPLL_out = 120MHz,

Integer Mode

—

JPLL_cyc

PLL period jitter (pk-

pk) 1,2,3

—

853

FPLL_out = 120MHz,

Fractional Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1,2,3

—

840

FPLL_out = 120MHz,

Integer Mode

—

JPLL_acc

PLL accumulated

jitter (pk-pk) 1,2,3

—

1680

FPLL_out = 120MHz,

Fractional Mode

—

1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter

specification is not valid with SSCG

2. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.

3. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .

11.4 Fast External Oscillator (FXOSC)

Table 42. Fast External Oscillator (FXOSC)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

FREQ_BYPASS

Input clock

frequency in bypass

mode 1

—

MHz

—

TRF_BYPASS

Input clock rise/fall

time in bypass

mode 1

—

CLKIN_DUTY_

BYPASS

Input clock duty

cycle in bypass

mode 1

47.5

—

52.5

—

FXOSC_CLK

output clock

frequency in crystal

mode

—

MHz

—

Table continues on the next page...

NXP Semiconductors

Clocking modules

S32K3xx Data Sheet, Rev. 8, 06/2023

Data Sheet: Technical Data

Preliminary Information for S32K3x8

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