23

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and

rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.

2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

CSB

OR

MBB

ENB

B0-B35

CLKB

IR

CLKA

CSA

5610 drw15

W/

RA

12

A0-A35

MBA

ENA

tCLK

tCLKH

tCLKL

tENS2

tENH

tA

tSKEW1

tCLK

tCLKH

tCLKL

tENS2

tENS2

tDS

tENH

tENH

tDH

To FIFO

Previous Word in FIFO Output Register

Next Word From FIFO

LOW

W/RB

HIGH

LOW

HIGH

LOW

HIGH

(1)

FIFO Full

tWFF

tWFF