IDT723663 datasheet(14/30 Pages) RENESAS

14 / 30 page

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

tSKEW2orgreaterafterthereadthatreducesthenumberofwordsinmemory

to[4,096/8,192-(Y+1)].Otherwise,thesubsequentsynchronizingclockcycle

may be the first synchronization cycle (see Figure 16).

MAILBOX REGISTERS

Two 36-bit bypass registers are on the IDT723663/723673 to pass

commandandcontrolinformationbetweenPortAandPortBwithoutputtingit

in queue. The Mailbox select (MBA, MBB) inputs choose between a mail

registerandaFIFOforaportdatatransferoperation.Theusablewidthofboth

the Mail1 and Mail2 Registers matches the selected bus size for Port B.

ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen

a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the

selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys

datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth

of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are

don’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusablewidth

oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t

careinputs.)

ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatotheMail2Register

when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If

the selected Port B bus size is 36 bits, the usable width of the Mail2 employs

datalinesB0-B35.IftheselectedPortBbussizeis18bits,thentheusablewidth

of the Mail2 Register employs data lines B0-B17. (In this case, B18-B35 are

don’tcareinputs.)IftheselectedPortBbussizeis9bits,thentheusablewidth

oftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35aredon’t

careinputs.)

Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)

LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.

Whendataoutputsofaportareactive,thedataonthebuscomesfromthe

FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe

mail register when the port Mailbox select input is HIGH.

TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition

on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB

HIGH.Fora36-bitbussize,36bitsofmailboxdataareplacedonB0-B35.For

an18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthiscase,

B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are

placed on B0-B8. (In this case, B9-B35 are indeterminate.)

TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition

on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA

HIGH.

Fora36-bitbussize,36bitsofmailboxdataareplacedonA0-A35.Foran

18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase,A18-

A35areindeterminate.)Fora9-bitbussize,9bitsofmailboxdataareplaced

on A0-A8. (In this case, A9-A35 are indeterminate.)

Thedatainamailregisterremainsintactafteritisreadandchangesonlywhen

new data is written to the register. The Endian select feature has no effect on

mailboxdata.Formailregisterandmailregisterflagtimingdiagrams,seeFigure

17 and 18.

BUS SIZING

The Port B bus can be configured in a 36-bit long word, 18-bit word, or 9-

bitbyteformatfordatareadfromtheFIFO.ThelevelsappliedtothePortBBus

Sizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbussize.

These levels should be static throughout FIFO operation. Both bus size

selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input

Ready flag is set HIGH, as shown in Figure 2.

TwodifferentmethodsforsequencingdatatransferareavailableforPortB

when the bus size selection is either byte-or word-size. They are referred to

asBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificantbyte

first).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-to-

HIGHtransitionofRS1selectstheendianmethodthatwillbeactiveduringFIFO

operation.BEisadon’tcareinputwhenthebussizeselectedforPortBislong

word.TheendianmethodisimplementedatthecompletionofReset,bythetime

the Full/Input Ready flag is set HIGH, as shown in Figure 2.

Only36-bitlongworddataiswrittentoorreadfromtheFIFOmemoryonthe

IDT723663/723673.Bus-matchingoperationsaredoneafterdataisreadfrom

the FIFO RAM. These bus-matching operations are not available when

transferringdataviamailboxregisters.Furthermore,boththeword-andbyte-

sizebusselectionslimitthewidthofthedatabusthatcanbeusedformailregister

operations.Inthiscase,onlythosebytelanesbelongingtotheselectedword-

or byte-size bus can carry mailbox data. The remaining data outputs will be

indeterminate.Theremainingdatainputswillbedon’tcareinputs.Forexample,

when a word-size bus is selected, then mailbox data can be transmitted only

betweenA0-A17andB0-B17.Whenabyte-sizebusisselected,thenmailbox

datacanbetransmittedonlybetweenA0-A8andB0-B8.(SeeFigures17and

18).

BUS-MATCHING FIFO READS

DataisreadfromtheFIFORAMin36-bitlongwordincrements.Ifalongword

bussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFOoutput

bytesappearontheselectedportionoftheFIFOoutputregister,withtherest

of the long word stored in auxiliary registers. In this case, subsequent FIFO

reads output the rest of the long word to the FIFO output register in the order

shown by Figure 2.

When reading data from FIFO in byte or word format, the unused B0-B35

outputsareindeterminate.

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