22

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.

2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.

Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)

CSA

W/

RA

MBA

FF

A0-A35

CLKB

EF

CSB

W/RB

MBB

ENA

ENB

B0-B35

CLKA

12

5610 drw14

tCLKH

tCLKL

tCLK

tENS2

tENS2

tENH

tENH

tDS

tDH

tSKEW1

tCLK

tCLKL

tENS2

tENH

tA

W1

FIFO Empty

LOW

HIGH

LOW

HIGH

LOW

tCLKH

W1

HIGH

(1)

tREF

tREF