JS28F320J3F75 datasheet(24/67 Pages) NUMONYX

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Datasheet

Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

7.0

AC Characteristics

Timing symbols used in the timing diagrams within this document conform to the

following convention.

Note:

Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that

refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV

(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s

data sheet, and is the address-to-data delay for subsequent page-mode reads.

Figure 7: Timing Signal Naming Convention

Table 10: Timing Signal Name Decoder

Signal

Code

State

Code

Address

High

Data - Read

Low

Data - Write

High-Z

Chip Enable (CE)

Low-Z

Output Enable (OE#)

Valid

Write Enable (WE#)

Invalid

Status (STS)

Reset (RP#)

Byte Enable (BYTE#)

Erase/Program/Block Lock

Enable (VPEN)

L Q V

Source Signal

Target State

Source State

Target Signal

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