RT3602AE datasheet(27/46 Pages) RICHTEK

27 / 46 page

RT3602AE

DS3602AE-00 August 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Phase Disable (Before POR)

The number of active phases is determined by the internal

circuitry that monitors the ISENxN voltages during startup.

Normally, the AUXI rail operates as a 2-phase PWM

controller. Pulling ISEN2N to VCC programs a 1-phase

operation. Before POR, VR detects whether the voltage

of ISEN2N is higher than “VCC

− 1V” to decide how many

phases should be active. Phase selection is only active

during POR. When POR = high, the number of active

phases is determined and latched. The unused ISENxP

pins are recommended to be connected to VCC and unused

PWM pins can be left floating.

POR

Chip

Enable

4.45V

0.7V

VCC

VTT

1.05V

Figure 8. POR Detection

VCC

POR

SVID Invalid

Invalid

Valid

2ms

Figure 9. Timing Chart for POR Process

Switching Frequency Setting

The RT3602AE is one kind of constant on-time control.

The patented CCRCOT (Constant Current Ripple COT)

technology can generate an adaptive on-time with input

voltage and VID code to obtain a constant current ripple,

so that the output voltage ripple can be controlled nearly

like a constant as different input and output voltages

change.

The Ton equation can be classified as below two regions

DAC

TON

DAC

TON

DAC

V0.9

1.2

15n

k(V

)

V0.9

1.08

15n

k(V

)

















where kTON is a coefficient which can be selected by

SET[1:3] pins for each VR rail. Table 3 and Table 6 show

the kTONcoefficient and ki gain setting for each VR rail on

the SET[1:3] pins.

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