RT3602AE datasheet(41/46 Pages) RICHTEK

41 / 46 page

RT3602AE

DS3602AE-00 August 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Under-Voltage Protection

When the VSEN pin voltage is 350mV less than VID, UVP

will be latched. When UVP latched, the both UGATEx

and LGATEx are pulled low. A 3

μs delay is used in UVP

detection circuit to prevent false trigger. Besides, the UVP

function is masked when dynamic VID transient occurs

and after dynamic VID transition, UVP is masked for 80

μs.

Design Step :

The RT3602AE Excel based design tool is available. Users

can contact your Richtek representative to get the

spreadsheet. Three MAIN design procedures of the

RT3602AE design, first step is loop design, second step

is pin setting design, and the last step is protection

settings. The following design example is to explain the

RT3602AE design procedure :

AUXI VR

VAUXI Specification

Input Voltage

19V

No. of Phase

Normal VID

1.35V

ICCMAX

ICC-Dyn

Load-Line

2.1m



Fast Slew Rate

37.5mV/

s

MAX Switching

Frequency

700kHz

The output filter requirements of VRTB specification are

as follows :

Output Inductor : 220nH/0.875m

Output Ceramic Capacitor: 47

μF (6pcs)

Output Ceramic Capacitor:10

μF (9pcs)

Loop Design :



On time setting: Using the specification, then can get

that tON is 108ns.

The kTON parameter can be calculated after the on-time

is decided.

DAC

TON

DAC

1.2μ V

t15n

k(V

)







Choosing the nearest on-time setting kTON = 1.1



Current sensor adopts lossless RC filter to sense current

signal in DCR. For getting an expected load transient

waveform RXCX time constant needs to match LX/DCRX.

CX = 0.47

μF, RNTC = 10kΩ and RP = 10kΩ are set, then



EQU

NTC

R //R



EQU

DCR







By using the design tool, RS and RX can be determined,

are equal to 220

Ω and 590Ω, respectively.



IMON resistor network design :

IMON

EQU

XEQU

∆V2.15k

R31.25k

ICCMAX DCR













Load-line design : 2.1m

Ω droop is requirement, because

DCR and ki are decided to 0.875m

Ω and 20,

respectively. The voltage loop Av gain is also can be

determined by following equation :

DCR

AR2





R1 = 10k

Ω is usually decided and here R2 is chosen to

37.4k

Ω.



Typical compensator design can use the following

equations to design C1 and C2 values

45.5pF

R1 π F





OUT

CESR

33pF





For Intel platform, in order to induce the band width to

enhance transient performance to meet Intel's criterion,

the zero location can be designed close to 1/10 of the

switching frequency or less than the 1/10 of switching

frequency.

RT3602AE bảng dữ liệu(PDF) 41 Page - Richtek Technology Corporation

RT3602AE bảng dữ liệu(HTML) 41 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL