RT3602AE datasheet(43/46 Pages) RICHTEK

43 / 46 page

RT3602AE

DS3602AE-00 August 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Loop Design :



On time setting: Using the specification, then can get

that tON parameter can be calculated after the on-time

is decided.

DAC

TON

DAC

1.2μ V

t15n

k(V

)







Choosing the nearest on-time setting kTON = 1.1



Current sensor adopts lossless RC filter to sense current

signal in DCR. For getting an expected load transient

waveform RXCX time constant needs to match LX/DCRX.

CX = 0.47

μF is set, then

R530

1μFDCR









IMON resistor network design : TL = 25

°C, TR = 50°C

and TH = 100oC are decided, NTC thermistor = 100k

@ 25oC,

β = 4485 and ICCMAX = 31A. RIMON1 =

16.74k

Ω, RIMON2 = 17.35kΩ and RIMON3 = 9.16kΩ can

be decided. The REQ (25

°C) = 31.78kΩ.



Load-line design: 3.1m

Ω droop is requirement, because

DCR and ki are decided to 0.875m

Ω and 2, respectively.

The voltage loop Av gain is also can be determined by

following equation :

IMON

DCR R





1 = 10kΩ is usually decided and here R2 is chosen to

42.2k

Ω.



Typical compensator design can use the following

equations to design C1 and C2 values

45.5pF

R1 π F





OUT

CESR

55pF





For intel platform, in order to induce the band width to

enhance transient performance to meet intel's criterion,

the zero location can be designed close to 1/10 of the

switching frequency or less than the 1/10 of switching

frequency.

Pin Setting Design :

SET1 resistor network design : From above designs,

parameters of kTON_AUXI and ki_AUXI are 1.1 and 20,

respectively. The AUXI_QR_TH is set to disable and

AUXI_QR_Width is designed as 0.7 x TON. And anti-

overshoot function is disabled for AUXI rail. By using

the information, the two equation can be listed by using

multi-function pin setting mechanism :

3.2

175.17mV

R1 R2





R1 R2

80μ

975.9mV

R1 R2







R1 = 222.86k

Ω and R2 = 12.91kΩ.



SET2 resistor network design : From above designs,

parameters of kTON_MAIN and ki_MAIN are 1.1 and 2,

respectively. The MAIN_QR_TH is set to 15mV and

MAIN_QR_Width is designed as 0.7 x TON. And anti-

overshoot function is disabled for MAIN rail. By using

the information, the two equation can be listed by using

multi-function pin setting mechanism :

3.2

575.56mV

R1 R2





R1 R2

80μ

1176.14mV

R1 R2







R1 = 81.74k

Ω and R2 = 17.93kΩ.



SET3 resistor network design: From above designs,

parameter of kTON_SA is 1.1. The DVID thresholds are

60mV, 15mV, and 60mV for MAIN, AUXI, and SA rail.

The force-non-zero VBOOT is setting as Intel VBOOT.

By using the information, the two equation can be listed

by using multi-function pin setting mechanism :

3.2

1326.3mV

R1 R2





R1 R2

80μ

875.86mV

R1 R2







R1 = 26.4k

Ω and R2 = 18.7kΩ.



TSEN_AUXI resistor network design : The ICCMAX of

MAIN rail is designed as 31A. And zero load-line function

for SA rail is disabled. By using the information, the

RT3602AE bảng dữ liệu(PDF) 43 Page - Richtek Technology Corporation

RT3602AE bảng dữ liệu(HTML) 43 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL