RT3602AE datasheet(42/46 Pages) RICHTEK

42 / 46 page

RT3602AE

www.richtek.com

DS3602AE-00 August 2017

is a registered trademark of Richtek Technology Corporation.

SA VR

VSA Specification

Input Voltage

19V

No. of Phase

Normal VID

1.05V

ICCMAX

ICC-Dyn

Load-Line

10.3m



Fast Slew Rate

37.5mV/

s

MAX Switching Frequency

800kHz

The output filter requirements of VRTB specification are

as follows :

Output Inductor: 820nH/6.7m

Output Ceramic Capacitor: 47

μF (4pcs)

Output Ceramic Capacitor:10

μF (8pcs)

Loop Design :



On time setting : Using the specification, then can get

that tON is 96ns.

The kTON parameter can be calculated after the on-time

is decided.

DAC

TON

DAC

1.2μ V

t15n

k(V

)







Choosing the nearest on-time setting kTON = 1.1

Current sensor adopts lossless RC filter to sense current

signal in DCR. For getting an expected load transient

waveform RXCX time constant needs to match LX/DCRX.

CX = 0.47

μF, RNTC = 4.7kΩ and Rp = 4.7kΩ are set,

then



EQU

NTC

R //R



EQU

DCR







By using the design tool, RS and RX can be determined,

are equal to 165

Ω and 280Ω, respectively.



IMON resistor network design :

IMON

EQU

XEQU

∆V2.15k

23.79k

ICCMAX DCR











VMAIN Specification

Input Voltage

19V

No. of Phase

Normal VID

1.35V

ICCMAX

ICC-Dyn

Load-Line

3.1m



Fast Slew Rate

37.5mV/

s

MAX Switching Frequency

700kHz

The output filter requirements of VRTB specification are

as follows :

Output Inductor: 220nH/0.875m

Output Bulk Capacitor: 330

μF/2V.4.5mΩ (1pcs)

Output Ceramic Capacitor: 47

μF (6pcs)

Output Ceramic Capacitor: 22

μF (7pcs)

Output Ceramic Capacitor:10

μF (2pcs)



Load-line design : 10.3m

Ω droop is requirement,

because DCR and ki are decided to 6.7m

Ω and 20,

respectively. The voltage loop Av gain is also can be

determined by following equation :

DCR





R1 = 10k

Ω is usually decided and here R2 is chosen to

58.5k

Ω.

Typical compensator design can use the following

equations to design C1 and C2 values

45.5pF

R1 π F





OUT

CESR

56pF





For Intel platform, in order to induce the band width to

enhance transient performance to meet Intel's criterion,

the zero location can be designed close to 1/10 of the

switching frequency or less than the 1/10 of switching

frequency.

MAIN VR

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