Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 4 of 40
INDT/R331B configurations
Mode
High-speed
Sideband
Low-speed
Sideband
Audio
Up to
VESA-/DTV-Mode
1
XX
X
/–
SXGA 24 color bits
2
–
X
X
UXGA 18 color bits
3
–
–
–
UXGA 18 color bits
4
X
X
X
720p (60fps)
5
X
X
X
1080i (30fps)
Table 1.2: INDT/R331B Video Configuration
Note: Implementation of video modes other than VESA or DTV/HDTV is possible. Special modes may need evaluation.
1.2 Pixel Interface
1.2.1 General Information
The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as
graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also
be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.
Figure 1.2: Pixel Interface
Signal
Tx
1
Rx
Description
PX_D[47:0]
IN
OUT
Configurable parallel pixel data interface
PX_CLK+
IN
OUT
Tx Pixel clock 24 – 161 MHz, diff + or single-ended
PX_CLK–
IN
OUT
Tx Pixel clock 24 – 161 MHz, diff –
PX_CLK
OUT
Rx Pixel clock 24 – 161 MHz
PX_CLK_OUT
OUT
Rx Pixel clock 24 – 161 MHz, de-jitter
PC_CLK_IN
IN
Rx Pixel clock 24 – 161 MHz, de-jitter
PX_HSYNC
IN
OUT
Pixel data framing – Horizontal sync pulse
PX_VSYNC
IN
OUT
Pixel data framing – Vertical sync pulse
PX_DE
IN
OUT
Pixel data framing – Data enable
Table 1.3: Pixel Interface Signals
1 Configurable to 3.3V or 1.8V input levels via VREF-pin.
Video
INDR
Receiver
Video
48
PX_CLK
PX_D[47:0]
PX_HSYNC
PX_VSYNC
PX_DE
48
PX_CLK+
PX_D[47:0]
PX_HSYNC
PX_CLK–
PX_VSYNC
PX_DE
INDT
Transmitter
Downstream
PX_CLK_OUT
PX_CLK_IN
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