Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 13 of 40
2.2 Configuration Vectors and Configuration Data
Four configuration vectors (cfg0 – cfg3, 4-bit each) must be loaded into the device through the low-speed sideband data
interfaces SB0 and SB2. The Tx and the Rx device must be connected via the downlink.
SB0 and SB2 sideband data are multiplexed and are also used for device configuration. After de-assertion of RESET#,
CFG_CYC is automatically being driven high and enables the configuration process.
The configuration select signals (CFG_SEL[3:0]) are provided sequentially at SB0 (INDT) respectively at SB2 (INDR).
These select signals enable e.g. an external logic which provides the configuration vectors (cfg0 – cfg3) via the
configuration signals CFG_D[3:0]. These are read at SB2 (INDT) respectively at SB0 (INDR).
Sequence
Vector
name
Configuration Select Signals
CFG_SEL[3:0]
Configuration vector
1
cfg0
0001
Requests configuration vector 0
2
cfg1
0010
Requests configuration vector 1
3
cfg2
0100
Requests configuration vector 2
4
cfg3
1000
Requests configuration vector 3
Table 2.1: Configuration Vector Sequence
Transmitter
Receiver
Configuration mode
(CFG_CYC = 1)
CFG_SEL[3:0]
CFG_D[3:0]
CFG_SEL[3:0]
CFG_D[3:0]
Normal mode
(CFG_CYC = 0)
SB0_D[3:0]
SB2_D[3:0]
SB2_D[3:0]
SB0_D[3:0]
Table 2.2: Pin Naming Multiplex Matrix
CFGEN
SYNC1/0
SDB
t>1ms
t>1ms
LOW
LOW
CFGDATA
SB0_D[3…0]
SB1_D[1…0]
For proper initialization of the upstream channel, the side band data input at the Rx needs to be kept low for >1ms after the
SYNC1/0 went high.
Figure 2.2 shows how to perform the configuration with external logic.
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