Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 32 of 40
4.4 INDR331B Receiver Signal Description
Pin Name
Pin
Dir
Type
Description
Link Interface
RX0+
B12
IN
CML
RX0–
B13
IN
CML
Serial Data Input (Downlink 0)
RX1+
B5
IN
CML
RX1–
B6
IN
CML
Serial Data Input (Downlink 1)
TX2+
A10
OUT
CML
TX2–
A9
OUT
CML
Serial Data Output (Uplink)
LOCK0
B10
OUT
LVTTL
Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked
LOCK1
B3
OUT
LVTTL
Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked
SYNC0
C1
OUT
LVTTL
HIGH when the Downlink 0 is frame synchronous
SYNC1
D1
OUT
LVTTL
HIGH when the Downlink 1 is frame synchronous
EQ
A2
IN
LVTTL
Selects the Downlink equalizer (LOW=OFF; HIGH=ON)
Pixel Interface
PX_CLK
R18
OUT
LVTTL
Pixel clock 24 – 161 MHz,
PX_CLK_IN
B2
IN
LVTTL
Pixel clock 24 – 161 MHz, de-jitter feedback
PX_CLK_OUT
P18
OUT
LVTTL
Pixel clock 24 – 161 MHz, de-jitter feedback
PX_D[47:0]
(see Table
4.12)
OUT
LVTTL
Configurable parallel pixel data interface
PX_HSYNC
N18
OUT
LVTTL
Pixel data framing – Horizontal sync pulse (active HIGH)
PX_VSYNC
N17
OUT
LVTTL
Pixel data framing – Vertical sync pulse (active HIGH)
PX_DE
P17
OUT
LVTTL
Pixel data framing – Data enable (active HIGH)
Sideband Interface
SB0_CLK
C18
OUT
LVTTL
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB0_D[3:0]
(CFG_D[3:0])
A16,A17,A
18,B18
IN
LVTTL
If CFG_CYC=0: Sideband Data Channel 0 Upstream Input
If CFG_CYC=1: Configuration data input
SB1_CLKI
G17
IN
LVTTL
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is
registered at rising edge.
SB1_CLKO
G18
OUT
LVTTL
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB1_ D[1:0]
F18,F17
IN
LVTTL
Sideband Data Channel 1 Upstream Input
SB2_CLK
E17
OUT
LVTTL
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB2_D[3:0]
(CFG_SEL[3:0])
C17,D18,
D17,E18
OUT
LVTTL
If CFG_CYC=0: Sideband Data Channel 2 Downstream Output
If CFG_CYC=1: Configuration vector output
SB3_CLK
M18
OUT
LVTTL
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB3_D[1:0]
K18,L18
OUT
LVTTL
Sideband Data Channel 3 Downstream Output
SB4_CLK
J18
OUT
LVTTL
Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB4_D[1:0]
H18,H17
OUT
LVTTL
Sideband Data Channel 4 Downstream Output
Audio Interface
AI_C0
E1
OUT
LVTTL
S/P-DIF Audio Channel 0
AI_C1
F1
OUT
LVTTL
S/P-DIF Audio Channel 1
AI_C2
G1
OUT
LVTTL
S/P-DIF Audio Channel 2
AI_C3
H1
OUT
LVTTL
S/P-DIF Audio Channel 3
Other Signals
RESET#
A1
IN
LVTTL
Asynchronous Hardware Reset (active LOW)
ERROR
B1
OUT
LVTTL
Pixel Clock Recovery Error
CFG_CYC
C2
OUT
LVTTL
Indicates that the configuration process is active
OSC
A3
IN
LVTTL
Reference Oscillator Input (see chapter 3.7)
CAP1
A15
IN
A
Loop filter pin Downlink 0
CAP2
B15
IN
A
Loop filter pin Downlink 0
CAP3
A8
IN
A
Loop filter pin Downlink 1
CAP4
B8
IN
A
Loop filter pin Downlink 1
Table 4.10: INDR331B Receiver Signals
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