Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 10 of 40
1.3.6 Sideband Interface Signals
Sideband
Signal
Dir
Description
SB0
SB0_CLK
OUT
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data
is provided aligned to rising edge.
SB0
SB0_D[3:0]
OUT
Sideband Data Channel 0 Upstream Output
SB1
SB1_CLK
OUT
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data
is provided aligned to rising edge.
SB1
SB1_D[1:0]
OUT
Sideband Data Channel 1 Upstream Output
SB2
SB2_CLK
OUT
Sideband Data Channel 2 Downstream Synchronous Clock Output.
Data is registered at rising edge.
SB2
SB2_D[3:0]
IN
Sideband Data Channel 2 Downstream Input
SB3
SB3_CLKI
IN
Sideband Data Channel 3 Downstream Asynchronous Clock Input.
Data is registered at rising edge.
SB3
SB3_CLKO
OUT
Sideband Data Channel 3 Downstream Synchronous Clock Output.
Data is registered at rising edge.
SB3
SB3_D[1:0]
IN
Sideband Data Channel 3 Downstream Input
SB4
3
SB4_CLKI
IN
Sideband Data Channel 4 Downstream Asynchronous Clock Input.
Data is registered at rising edge.
SB4
3
SB4_CLKO
OUT
Sideband Data Channel 4 Downstream Synchronous Clock Output.
Data is registered at rising edge.
SB4
3
SB4_D[1:0]
IN
Sideband Data Channel 4 Downstream Input.
Table 1.7: Sideband Interface Signals (INDT, Transmitter)
Sideband
Signal
Dir
Description
SB0
SB0_CLK
OUT
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data
is registered at rising edge.
SB0
SB0_D[3:0]
IN
Sideband Data Channel 0 Upstream Input
SB1
SB1_CLKI
IN
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data
is registered at rising edge.
SB1
SB1_CLKO
OUT
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data
is registered at rising edge.
SB1
SB1_D[1:0]
IN
Sideband Data Channel 1 Upstream Input
SB2
SB2_CLK
OUT
Sideband Data Channel 2 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
SB2
SB2_D[3:0]
OUT
Sideband Data Channel 2 Downstream Output
SB3
SB3_CLK
OUT
Sideband Data Channel 3 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
SB3
SB3_D[1:0]
OUT
Sideband Data Channel 3 Downstream Output
SB4
3
SB4_CLK
OUT
Sideband Data Channel 4 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
SB4
3
SB4_D[1:0]
OUT
Sideband Data Channel 4 Downstream Output.
Table 1.8: Sideband Interface Signals (INDR, Receiver)
3 Sideband Data Channel 4 (SB4) only available with INDT/R330B
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