36 / 40 page

Preliminary Data Sheet
INDT/R166B
INDT/R331B
Date: 2005-03-14 Revision: 0.1
Page 36 of 40
5.3 INDT331B Transmitter
1234
5678
9
10
11
12
13
14
15
16
17
18
A GND_
IO
RESET#
OSC
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
CAP3
RX2–
RX2+
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
CAP1
SB0_
D3
SB0_
D2
SB0_
D1
B
CFG_
CYC
ERROR
LOCK1
GND_
A0
TX1+
TX1–
GND_
A0
CAP4
VCC_
SX
LOCK0
GND_
A0
TX0+
TX0–
GND_
A0
CAP2
GND_
IO
GND_
IO
SB0_
D0
C
NC
SYNC2
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
SX
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
IO
SB2_
D3
SB0_
CLK
D AI_C1 AI_C0
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
SB2_
D1
SB2_
D2
E AI_C2
GND_
IO
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
IO
SB2_
CLK
SB2_
D0
F AI_C3
GND_
CORE
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
IO
GND_
IO
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
IO
GND_
IO
SB1_
D0
SB1_
D1
G PX_D0
VCC_
IO
VCC_
CORE
VCC_
CORE
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
IO
SB3_
D1
SB1_
CLK
H PX_D1
VCC_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
SB3_
CLKO
SB3_
D0
J PX_D2
GND_
CORE
GND_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
CORE
VCC_
CORE
VCC_
CORE
SB3_
CLKI
K PX_D3
GND_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
GND_
CORE
SB4_
D1
L PX_D4
GND_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
GND_
IO
SB4_
D0
M PX_D5
VCC_
IO
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
VCC_
IO
SB4_
CLKO
N PX_D6
VCC_
CORE
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
IO
SB4_
CLKI
VREF
P PX_D8 PX_D7
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
PX_DE
PX_
VSYNC
R PX_D10 PX_D9
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
PX_
HSYNC
PX_
CLK–
T PX_D11
GND_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
PX_D47
PX_
CLK+
U PX_D12
GND_
IO
PX_D15 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D39 PX_D41 PX_D45 PX_D46
V PX_D13 PX_D14 PX_D16 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D40 PX_D42 PX_D43 PX_D44
Table 5.3: INDT331B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View)