DP83255AVF datasheet(74/96 Pages) NSC

tên linh kiện	DP83255AVF

Giải thích chi tiết về linh kiện	PLAYER Device (FDDI Physical Layer Controller)

PDF	96 Pages

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nhà sản xuất	NSC [National Semiconductor (TI)]

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74 / 96 page

60 Pin Descriptions (Continued)

CLOCK INTERFACE

The Clock Interface consists of 125 MHz and 125 MHz clocks used by the PLAYER device The clocks are generated by either

the Clock Distribution Device or Clock Recovery Device

Symbol

Pin No

Description

LBC

Local Byte Clock

A TTL 125 MHz 50% duty cycle input clock from the Clock

Distribution Device The Local Byte Clock is used by the PLAYER device’s internal

CMOS logic and to latch incomingoutgoing data of the Control Bus Interface Port A

Interface Port B Interface and other miscellaneous IOs

RXCa

Receive Bit Clock

Differential 100k ECL 125 MHz clock input signals from the Clock

Recovery Device The Receive Bit Clock is used by the Serial Interface to latch the

RXCb

Receive Data (RXDg)

TXCa

Transmit Bit Clock

Differential 100k ECL 125 MHz clock input signals from the Clock

Distribution Device The Transmit Bit Clock is used by the Serial Interface to latch the

TXCb

Transmit Data (TXDg)

TBCa

Transmit Byte Clock

Differental 100k ECL 125 MHz clock input signals from the

Clock Distribution Device The Transmit Byte Clock is used by the PLAYER device’s

TBCb

internal Shift Register Block

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