DP83255AVF datasheet(48/96 Pages) NSC

48 / 96 page

50 Registers (Continued)

USER DEFINABLE REGISTER (UDR)

The User Definable Register is used to monitor and control events which are external to the PLAYER device

The value of the Sense Bits reflects the asserteddeasserted state of their corresponding Sense pins On the other hand the

Enable bits assertdeassert the Enable pins

ACCESS RULES

ADDRESS

READ

WRITE

17h

Always

RES

EB1

EB0

SB1

SB0

Bit

Symbol

Description

SB0

SENSE BIT 0

This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (ie SP0 e VCC) for a minimum of

160 ns Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus

Interface even if the signal is deasserted This ensures that the Control Bus Interface will record the

source of events which can cause interrupts in a traceable manner

SB1

SENSE BIT 1

This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (ie SP1 e VCC) for a minimum of

160 ns Once the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus

Interface even if the signal is deasserted This ensures that the Control Bus Interface will record the

source of events which can cause interrupts in a traceable manner

EB0

ENABLE BIT 0

The Enable Bit 0 allows control of external logic through the Control Bus Interface The

User Definable Enable Pin 0 (EP0) is asserteddeasserted by this bit

0 EP0 is deasserted (ie EP0 e GND)

1 EP0 is asserted (ie EP0 e VCC)

EB1

ENABLE BIT 1

This bit allows control of external logic through the Control Bus Interface The User

Definable Enable Pin 0 (EP0) is asserteddeasserted by this bit

0 EP1 is deasserted (ie EP1 e GND)

1 EP1 is asserted (ie EP1 e VCC)

D4 – 7

RES

RESERVED

Reserved for future use The reserved bit is set to 0 during the initialization process

(ie RST e GND)

Note

Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the

PLAYER device

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