DP83255AVF datasheet(32/96 Pages) NSC

32 / 96 page

50 Registers (Continued)

CURRENT RECEIVE STATE REGISTER (CRSR)

The Current Receive State Register represents the current line state being detected by the Receiver Block Once the Receiver

Block recognizes a new Line State the bits corresponding to the previous line state are cleared and the bits corresponding to

the new line state are set

During the reset process (RST e GND) the Receiver Block is forced to Line State Unknown (ie the Line State Unknown bit

(LSU) is set to 1)

ACCESS RULES

ADDRESS

READ

WRITE

08h

Always

Write Reject

RES

LSU

LS2

LS1

LS0

Bit

Symbol

Description

D0 D1

LS0 LS1

LINE STATEk0 1 2l

These bits represent the current Line State being detected by the Receiver

Block Once the Receiver Block recognizes a new line state the bits corresponding to the previous

LS2

line state are cleared and the bits corresponding to the new line state are set

LS2

LS1

LS0

000

Active Line State (ALS)

Received a JK

symbol pair (11000 10001) and possibly

followed by data symbols

001

Idle Line State (ILS)

Received a minimum

of two consecutive Idle symbol pairs (11111

11111)

010

No Signal Detect (NSD)

The Signal Detect

pin (TTLSD) has been deasserted indicating

that the Clock Recovery Device is not

receiving data from the Fiber Optic Receiver

011

Reserved

Reserved for future use

100

Master Line State (MLS)

Received a

minimum of 8 consecutive Halt-Quiet symbol

pairs (00100 00000)

101

Halt Line State (HLS)

Received a minimum

of 8 consecutive Halt symbol pairs (00100

00100)

110

Quiet Line State (QLS)

Received a

minimum of 8 consecutive Quiet symbol pairs

(00000 00000)

111

Noise Line State (NLS)

Detected a

minimum of 16 noise events Refer to the

Receiver Block for further information on

noise events

LSU

LINE STATE UNKNOWN

The Receiver Block has not detected the minimum conditions to enter a

known line state When the Line State Unknown bit is set LSk20l represent the most recently

known line state

RES

RESERVED

Reserved for future use The reserved bit is set to 0

Note

Users are discouraged from using this bit An attempt to write into this bit will cause the PLAYER device to ignore

the Control Bus write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition

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