22

105 Hardware Specifications

Preliminary/Subject to Change without Notice

1.6.5.1 Internal Package Conduction Resistance

For this C4/CBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows:

•

The die junction-to-case thermal resistance

•

The die junction-to-lead thermal resistance

These parameters are shown in Table 11. In this C4/CBGA package, the silicon chip is exposed; therefore,

the package “case” is the top of the silicon.

Figure 14 provides a simplified thermal network in which a C4/CBGA package is mounted to a printed-

circuit board.

Figure 14. C4/CBGA Package Mounted to a Printed-Circuit Board

1.6.5.2 Board and System-Level Modeling

A common figure-of-merit used for comparing the thermal performance of various microelectronic

packaging technologies is the junction-to-ambient thermal resistance. The final chip-junction operating

temperature is not only a function of the component-level thermal resistance, but the system-level design

and its operating conditions. In addition to the component’s power dissipation, a number of factors affect

the final operating die-junction temperature. For example, these factors might include airflow, board

population, heat sink efficiency, heat sink attach, next-level interconnect technology, and system air

temperature rise.

Table 11. Thermal Resistance

Thermal Metric

Effective Thermal Resistance

Junction-to-case thermal resistance

0.133

°C/W

Junction-to-lead (ball) thermal resistance

3.8

°C/W

External Resistance

External Resistance

Secondary Heat Transfer Path

Primary Heat Transfer Path

Internal Resistance

(Note the internal versus external package resistance)

Radiation

Convection

Radiation

Convection

Heat Sink

Silicon

C4 Package

Printed-Circuit Board

Heat Sink Attach

Package Leads/Ball

Chip Junction

Underfill

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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