STM32C011F6U6 datasheet(17/94 Pages) STMICROELECTRONICS

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DS13866 Rev 3

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STM32C011x4/x6

Functional overview

•

Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

–

32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

–

32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

•

Peripheral clock sources: several peripherals ( I2S, USARTs, I2C, ADC) have their

own clock independent of the system clock.

•

Clock security system (CSS): in the event of HSE or LSE clock failure, the system

clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software

interrupt is generated. The CCS feature can be enabled by software.

•

Clock output:

–

MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

–

LSCO (low speed clock output) provides LSI or LSE in all low-power modes .

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 48 MHz at maximum.

3.10

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11

Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 3 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

•

Single-AHB master

•

Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

•

Access, as source and destination, to on-chip memory-mapped devices such as flash

memory, SRAM, and AHB and APB peripherals

•

All DMA channels independently configurable:

–

Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

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