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STM32C011F6U6 bảng dữ liệu(PDF) 75 Page - STMicroelectronics

tên linh kiện STM32C011F6U6
Giải thích chi tiết về linh kiện  Arm® Cortex®-M0 32-bit MCU, 32 KB Flash, 6 KB RAM,2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32C011F6U6 bảng dữ liệu(HTML) 75 Page - STMicroelectronics

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STM32C011x4/x6
Electrical characteristics
79
Figure 22. SPI timing diagram - slave mode and CPHA = 0
th(MI)
Data input hold time
Master mode
2
-
-
ns
th(SI)
Slave mode
3
-
-
ns
ta(SO)
Data output access
time
Slave mode
9
-
34
ns
tdis(SO)
Data output disable
time
Slave mode
9
-
16
ns
tv(SO)
Data output valid time
Slave mode
2.7 V < VDD < 3.6 V
-10
16
ns
Slave mode
2 V < VDD < 3.6 V
-10
22
tv(MO)
Master mode
-
3
5.5
ns
th(SO)
Data output hold time
Slave mode
2 V < VDD < 3.6 V
8-
-
ns
th(MO)
Master mode
1.5
-
-
ns
1. Evaluated by characterization – Not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Table 61. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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