STM32C011F6U6 datasheet(15/94 Pages) STMICROELECTRONICS

15 / 94 page

DS13866 Rev 3

15/94

STM32C011x4/x6

Functional overview

stop. The HSI48 can be restarted by a peripheral with wake-up capability requiring

HSI48.

The LSE and LSI can be kept running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as

system clock.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The regulator is switched off to power down VCORE domain.

The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The

RTC is switched off.

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost, except for 16-bit backup

registers whose contents are kept.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge), or when a failure

is detected on LSE (CSS on LSE).

•

Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the VCORE domain. The HSI48 and LSI RC-

oscillators and HSE crystal oscillator are also powered down. The RTC is off.

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode.

SRAM and register contents are lost.

The device exits Shutdown mode upon external reset event (NRST pin), or wakeup

event (WKUP pin, configurable rising or falling edge).

3.7.5

Reset mode

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.8

Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

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