| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
HC708KL8GRS/D bảng dữ liệu(PDF) 77 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
HC708KL8GRS/D bảng dữ liệu(HTML) 77 Page - NXP Semiconductors |
|
77 / 246 page ![]() System Integration Module (SIM) MC68HC708KL8 — Rev. 2.1 General Release Specification Freescale Semiconductor System Integration Module (SIM) 77 Table 8-1 shows the internal signal names used in this section. 8.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 8-3. Figure 8-3. SIM Clock Signals Table 8-1. Signal Name Conventions Signal Name Description CGMXCLK Buffered OSC1 from the oscillator CGMOUT The CGMXCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = CGMXCLK divided by four) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal ÷ 2 BUS CLOCK GENERATORS SIM SIM COUNTER FROM OSCILLATOR FROM OSCILLATOR CGMOUT CGMXCLK |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |