XIO2000 datasheet(121/150 Pages) TI

121 / 150 page

Memory-Mapped TI Proprietary Register Space

109

November 2005

SCPS097B

Memory-Mapped TI Proprietary Register Space

The programming model of the memory-mapped TI proprietary register space is unique to this device. These

custom registers are specifically designed to provide enhanced features associated with upstream

isochronous applications.

All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated

power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST or the

internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,

GRST, or the internally-generated power-on reset.

Table 6−1. Device Control Memory Window Register Map

OFFSET

Upstream isochrony capabilities

Revision ID

Device control map ID

00h

Reserved

Upstream isochrony control

04h

Reserved

Upstream isochronous window 0 control

08h

Upstream isochronous window 0 base address

0Ch

Upstream isochronous window 0 limit

10h

Reserved

Upstream isochronous window 1 control

14h

Upstream isochronous window 1 base address

18h

Upstream isochronous window 1 limit

1Ch

Reserved

Upstream isochronous window 2 control

20h

Upstream isochronous window 2 base address

24h

Upstream isochronous window 2 limit

28h

Reserved

Upstream isochronous window 3 control

2Ch

Upstream isochronous window 3 base address

30h

Upstream isochronous window 3 limit

34h

Reserved

38h−3Ch

GPIO data†

GPIO control†

40h

Serial-bus control and status†

Serial-bus slave address†

Serial-bus word address†

Serial-bus data†

44h

Serial IRQ edge control†

Reserved

Serial IRQ mode control†

48h

Reserved

Serial IRQ status

4Ch

† One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

6.1

Device Control Map ID Register

The device control map ID register identifies the TI proprietary layout for this device control map. The value

01h identifies this as a PCI Express-to-PCI bridge supporting upstream isochronous capabilities.

Device control memory window register offset:

00h

Read-only

Default value:

01h

BIT NUMBER

RESET STATE

XIO2000 bảng dữ liệu(PDF) 121 Page - Texas Instruments

XIO2000 bảng dữ liệu(HTML) 121 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL