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IO-Link physical layer

9.1

UART frame

Table 20. UART frame definition

Bit#

Significance

Level

START

LSB

MSB

PARITY

STOP

A logic '1' is transmitted as a low level on the CQ line, and a logic '0' is transmitted as a high level on the line. The

idle state for the CQ line is low.

Even parity is used, that is, there is always an even number of logical '1' bits in the 9 bit concatenation of the data

bits b[7:0] and the parity bit.

9.2

M-sequence interpretation

The data direction is derived from the MSB of the first octet of the master message, M-sequence control (MC),

where a ‘1’ denotes a read operation and a '0' a write.

Table 21. M-sequence control (MC) octet

MSB

LSB

R/W

Comm chan.

Address

The M-sequence type is derived from bits [7:6] of the second octet of the master message, “Checksum/

Msequence type” (CKT), which have permissible values of 2'b00, 2'b01, or 2'b10, and denotes whether the

structure of the message is of Type 0, Type 1 or Type 2.

Table 22. Checksum/M-sequence type (CKT) octet

MSB

LSB

M-seq. type

Checksum

The total length of the received M-sequence is determined according to Table 23 and is dependent on the

M-sequence type and on the transfer direction (READ or WRITE).

L6364

IO-Link physical layer

DS13363 - Rev 4

page 24/60

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