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L6364 bảng dữ liệu(PDF) 14 Page - STMicroelectronics |
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L6364 bảng dữ liệu(HTML) 14 Page - STMicroelectronics |
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14 / 60 page ![]() 7 DIO pin The DIO pin is a fully protected I/O which is driven or sampled independently via SPI. This pin may be operated in one of two modes: • JOIN mode (DCTL:DIO bit = '0'). This is the default configuration for DCTL:DIO bit. The DIO/CQ outputs function together to provide a single, double drive strength, IO-Link conformal output. The outputs, DIO and CQ, must be externally shorted together. When in this mode, the DCTL:HS and DCTL:LS no longer have any effect on the output state. • DIO mode (DCTL:DIO bit = '1'). The DIO line functions as independent high voltage digital input output pin. Setting bit DCTL:IEN in this mode, enables a signal level change interrupt, informing the microcontroller that a level change has occurred on the DIO line. 7.1 DIO mode output control In DIO mode there are two alternatives for controlling the pin output state: via SPI (DCTL:EXT reset) or directly via pin CTLD (DCTL:EXT set). Table 16 and Table 17 show how the output is controlled in both cases respectively. Table 16. DIO control via SPI-DCTL:EXT=’0’ Mode DCTL:HS DCTL:LS DIO Channel Output State Off 0 0 HiZ Low 0 1 0 High 1 0 1 Illegal 1 1 HiZ If bit DCTL:EXT is set, bits DCTL:HS and DCTL:LS function as configuration bits, which configure the DIO output to be a PNP, NPN or Push-Pull driver. Table 17. Direct DIO control via pin CTLD – DCTL:EXT=’1’ DIO Channel Output State Mode DCTL:HS DCTL:LS CTLD=’1’ CTLD=’0’ Inactive 0 0 HiZ HiZ NPN 0 1 0 HiZ PNP 1 0 1 HiZ Push-Pull 1 1 1 0 The high- and low-side switches are identical and have an on-state resistance of RSW. Any inactive switch acts as a Zener diode limiting the voltage on the DIO line to VZEN above VVPLUS (high-side switch), or VZEN below GND (low-side switch). This allows rapid switch-off for inductive loads. The DIO data level is monitored for signals, filtering out pulses with a duration of less than (1/16) * TBIT, see Table 5. The decision threshold for the DIO data level is determined by the CFG:RF bit. Where this is '0', the IO-link standard absolute levels are used, and where the bit is '1' the threshold is referred to VVPLUS/1.8. L6364 DIO pin DS13363 - Rev 4 page 14/60 |
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